Once semiconductor devices on semiconductor wafers have been fabricated, they must be packaged in order to actually be used. The individual dies on the wafers are separated from one another, and then are typically put in a protective package. They may also be mounted onto the surface of a ceramic substrate as part of a hybrid circuit, put into a large package with other chips as part of a multi-chip module (MCM), or be connected directly on board a printed circuit or chip-on-board (COB). However, packaging the wafers individually into protective packages is still the most common back-end process.
FIG. 1 shows an example of a partially exposed packaged chip 100. The packaged chip 100 includes a die-attachment area 102. This is typically located in the center of the packaged chip 100, and is where the chip 114, or die, is securely attached into the package. The die-attachment area 102 may have an electrical connection that services to connect the back of the chip 114 to the rest of the lead system.
The packaged chip 100 also includes a metal lead system. The system inner connections are referred to as inner leads, such as the inner lead 108, bonding lead tips, or bond fingers. The inner leads are generally the narrowest portions of the lead system. The leads become progressively wider, ending outside the package. These portions of the lead system are called outer leads, such as the outer lead 106.
The lead system is connected to the chip 114 usually via bonding wires, such as the bonding wire 104 connecting to bonding pads of the chip 114, such as the bonding pad 112. Besides bonding wires, bonding balls and other types of electrical connections can be used. The entire chip 114 is enclosed in an enclosure 110. The enclosure 110 provides protection and heat-dissipation functions, and may be hermetically or non-hermetically sealed.
For the bonding wires or other types of electrical connections to successfully bond to the bonding pads of the chip, which can be generally defined as the (metal) electrical terminals on the chip used for connection to the package electrical system, the bonding pads must be free from contamination. Poor bonding pad surface cleanliness can result in pad delamination, as well as electrical connection pull or shear failure. This can reduce packaged chip yield, and/or cause failure once the package chip has been deployed into the field, such as being sold to a customer, and so on.
Bonding pad cleanliness has traditionally been tested by x-ray photoelectron spectroscopy (XPS), which is a technique for studying semiconductor surfaces. In XPS, a beam of x-rays is incident on the semiconductor surface. The x-rays transfer their energy to electrons in the semiconductor, which enables the electrons to escape from the surface. Measuring the energy of the escaped electrons allows a determination of the chemical identity of the atoms from which they came. This energy can be correlated to whether the electrons came from contamination, from the metal of the bonding pad itself, and so on.
However, XPS has a number of disadvantages when used for determining metal surface cleanliness, such as bonding pad surface cleanliness. It cannot be used as an in-line monitoring technique to monitor all or substantially all of the bonding pads of semiconductor dies. This is because XPS is a destructive process, and ends up destroying the bonding pad that it is examining. Therefore, XPS can only be performed on a sample basis, and not on all the chips that are to be packaged.
Furthermore, XPS requires a relatively large minimum testing area, such as 200 micron by 200 micron. However, as chips have become progressively smaller, their bonding pads are also becoming progressively smaller, and it is anticipated that bonding pads as small as 80 micron by 80 micron may become commonplace. As a result, XPS cannot be used to monitor such small bonding pads, since the sizes of these pads are less than the minimum area required by XPS.
Therefore, there is a need for a metal surface cleanliness monitoring technique that overcomes these disadvantages. Specifically, such a monitoring technique should not be a destructive process, so that in-line monitoring can be performed. The monitoring technique should also be able to be performed relative to a small minimum testing area, such as 80 micron by 80 micron. For these and other reasons, there is a need for the present invention.